AO4454 100v n-channel mosfet sdmos tm general description product summary v ds i d (at v gs =10v) 6.5a r ds(on) (at v gs =10v) < 36m w r ds(on) (at v gs = 7v) < 43m w 100% uis tested 100% r g tested symbol v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jl 2 t a =70c junction and storage temperature range -55 to 150 c thermal characteristics units parameter typ max c/w r q ja 31 59 40 v 25 gate-source voltage drain-source voltage 100 the AO4454 is fabricated with sdmos tm trench technology that combines excellent r ds(on) with low gate charge.the result is outstanding efficiency with co ntrolled switching behaviar. this universal technology is we ll suited for pwm, load switching and general purpose applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 100v mj avalanche current c 39 a 28 a i d 6.5 5.3 46 t a =25c t a =70c power dissipation b p d avalanche energy l=0.1mh c pulsed drain current c continuous drain current t a =25c w 3.1 maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 16 75 24 maximum junction-to-ambient a soic-8 top view bottom view d d d d s s s g g ds rev1: november 2010 www.aosmd.com page 1 of 6
AO4454 symbol min typ max units bv dss 100 v v ds =100v, v gs =0v 10 t j =55c 50 i gss 100 na v gs(th) gate threshold voltage 2.8 3.4 4 v i d(on) 46 a 30 36 t j =125c 56 67 35.5 43 m w g fs 20 s v sd 0.68 1 v i s 4 a c iss 950 1180 1450 pf c oss 77 110 145 pf c rss 21 36 50 pf r g 0.35 0.7 1.05 w q g (10v) 15 19 23 nc q gs 5.5 7 8.5 nc q gd 3.5 6.3 9 nc t d(on) 10 ns t r 7.2 ns t d(off) 15 ns t f 7 ns t rr 11 16 21 ns q rr 35 50 65 nc components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. body diode reverse recovery charge i f =6.5a, di/dt=500a/ m s maximum body-diode continuous current input capacitance output capacitance turn-on delaytime dynamic parameters turn-on rise time turn-off delaytime v gs =10v, v ds =50v, r l =6.7 w , r gen =3 w gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time total gate charge v gs =10v, v ds =50v, i d =6.5a gate source charge gate drain charge m w i s =1a,v gs =0v v ds =5v, i d =6.5a v gs =7v, i d =6a forward transconductance diode forward voltage r ds(on) static drain-source on-resistance i dss m a v ds =v gs i d =250 m a v ds =0v, v gs = 25v zero gate voltage drain current gate-body leakage current electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions body diode reverse recovery time drain-source breakdown voltage on state drain current i d =250 m a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =6.5a reverse transfer capacitance i f =6.5a, di/dt=500a/ m s v gs =0v, v ds =50v, f=1mhz switching parameters a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the value in any given application depends on the user' s specific board design. b. the power dissipation p d is based on t j(max) =150c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150c. ratings are based on low frequency and duty cycles to keep initialt j =25c. d. the r q ja is the sum of the thermal impedence from junction to lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedence which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150c. the soa curve provides a single pulse ratin g. rev 1: november 2010 www.aosmd.com page 2 of 6
AO4454 typical electrical and thermal characteristics 17 52 10 0 18 40 0 20 40 60 3 4 5 6 7 8 9 v gs (volts) figure 2: transfer characteristics (note e) i d (a) 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m w ww w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =4.5v i d =6a v gs =10v i d =6.5a 20 28 36 44 52 60 68 6 7 8 9 10 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m w ww w ) 25c 125c v ds =5v v gs =7v v gs =10v i d =6.5a 25c 125c 0 10 20 30 40 50 60 0 1 2 3 4 5 v ds (volts) fig 1: on-region characteristics (note e) i d (a) 6v 7v 8v 10v v gs =5v rev 1: november 2010 www.aosmd.com page 3 of 6
AO4454 typical electrical and thermal characteristics 0 2 4 6 8 10 0 5 10 15 20 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 200 400 600 800 1000 1200 1400 1600 0 10 20 30 40 50 60 70 80 90 100 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss c oss c rss v ds =50v i d =6.5a 10 100 0.000001 0.00001 0.0001 time in avalanche, t a (s) figure 9: single pulse avalanche capability (note c) i ar (a) peak avalanche current t a =25c t a =150c t a =100c t a =125c 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 11: single pulse power rating junction-to-am bient (note f) power (w) t a =25c 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 1000 v ds (volts) i d (amps) figure 10: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150c t a =25c 100 m s 10ms rev 1: november 2010 www.aosmd.com page 4 of 6
AO4454 typical electrical and thermal characteristics 40 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 12: normalized maximum transient thermal imp edance (note f) z q qq q ja normalized transient thermal resistance single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse r q ja =75c/w 0 30 60 90 120 150 0 5 10 15 20 25 30 i s (a) figure 13: diode reverse recovery charge and peak current vs. conduction current q rr (nc) 0 5 10 15 20 25 30 i rm (a) di/dt=800a/ m s 125oc 125oc 25oc 25oc q rr i rm 0 30 60 90 120 150 0 200 400 600 800 1000 di/dt (a/ m mm m s) figure 15: diode reverse recovery charge and peak current vs. di/dt q rr (nc) 0 5 10 15 20 25 30 i rm (a) 125oc 125oc 25oc 25oc i s =20a q rr i rm 0 2 4 6 8 10 12 14 16 18 20 22 24 0 5 10 15 20 25 30 i s (a) figure 14: diode reverse recovery time and softness factor vs. conduction current t rr (ns) 0 0.5 1 1.5 2 2.5 3 s di/dt=800a/ m s 125oc 125oc 25oc 25oc t rr s 0 3 6 9 12 15 18 21 24 27 30 0 200 400 600 800 1000 di/dt (a/ m mm m s) figure 16: diode reverse recovery time and softness factor vs. di/dt t rr (ns) 0 0.5 1 1.5 2 2.5 s 125oc 25oc 25oc 125o i s =20a t rr s rev 1: november 2010 www.aosmd.com page 5 of 6
AO4454 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev 1: november 2010 www.aosmd.com page 6 of 6
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